An
article on Physical Design
BY
HARISH. K
Brindavan
College of Engineering Bangalore
Department of Electronics &
Communication Engg
In integrated circuit design, physical
design is a step in the standard design cycle which follows after the circuit
design. At this step, circuit representations of the components
(devices and interconnects) of the design are converted into geometric
representations of shapes which, when manufactured in the corresponding layers
of materials, will ensure the required functioning of the components. This
geometric representation is called integrated circuit layout. This step is
usually split into several sub-steps, which include both design and
verification and validation of the layout. Modern day Integrated Circuit (IC) design is split up into
Front-end design using HDL's, Verification and Back-end Design
or Physical Design. The next step after Physical Design is the
Manufacturing process or Fabrication Process that is done in the Wafer
Fabrication Houses. Fab-houses fabricate designs onto silicon dies which are
then packaged into ICs. Each of the phases mentioned above have Design Flows
associated with them. These Design Flows lay down the process and
guide-lines/framework for that phase. Physical Design flow uses the technology
libraries that are provided by the fabrication houses. These technology files
provide information regarding the type of Silicon wafer used, the
standard-cells used, the layout rules (like DRC in VLSI).
At 40nm and 28nm, lithographic
limitations and atomistic doping greatly increase the burden on the design
methodology. Variations are up, sensitivities are up, and at the same time the
designs themselves are larger and encompass more building blocks than before.
From a methodology point of view,
focus areas like signal integrity, power integrity, DFM and DFT all take on new
complexities as a result. Open-Silicon’s 40nm and 28nm reference flows leverage
the best in learning from Open-Silicon’s multiple EDA and foundry partners to
put together a solution designed to meet Open-Silicon’s benchmark performance
in terms of predictability and reliability
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